View LT4256-3_299462.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LT4256-3 Positive High Voltage Hot Swap Controller with Open-Circuit Detect
FEATURES
s s s s s s
DESCRIPTIO
s s s s
Allows Safe Board Insertion and Removal from a Live Backplane Controls Supply Voltage from 10.8V to 80V Foldback Current Limiting Open Circuit and Overcurrent Fault Detect Drives an External N-Channel MOSFET Automatic Retry or Latched Off Operation After Overcurrent Fault Programmable Supply Voltage Power-Up Rate Open MOSFET Detection 1% Over and Undervoltage Detection Accuracy Available in a 16-Lead SSOP Package
The LT(R)4256-3 is a high voltage Hot Swap controller that allows a board to be safely inserted and removed from a live backplane. An internal driver controls the high side N-channel MOSFET gate for supply voltages ranging from 10.8V to 80V. The part features an open-circuit detect (OPEN) output that indicates abnormally low load current conditions. The LT4256-3 also features an adjustable analog foldback current limit. If the supply remains in current limit for more than a programmable time, the N-channel MOSFET shuts off, the PWRGD output asserts low and the LT4256-3 either automatically restarts after a time-out delay or latches off until the UV pin is cycled low (depending on the status of the RETRY pin). The PWRGD output indicates when the output voltage rises above a programmed level. An external resistor string from VCC provides programmable undervoltage and overvoltage protection. The LT4256-3 is available in a 16-lead SSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation.
APPLICATIO S
s s s s s
s
Hot Board Insertion Electronic Circuit Breaker/Power Bussing Industrial High Side Switch/Circuit Breaker 24V/48V Industrial/Alarm Systems Ideally Suited for 12V, 24V and 48V Distributed Power Systems 48V Telecom Systems
TYPICAL APPLICATIO
VIN 48V SMAT70A (SHORT PIN) 64.9k UV 0.01F 4.02k OV 4.02k OPEN TIMER GND 33nF GND VCC 0.020
48V, 2A Hot Swap Controller
IRF540
+
CMPZ5241BS 11V SENSE 10 GATE LT4256-3 VOUT FB 100 10nF 36.5k 51k CL
VOUT 48V 2A
VIN 50V/DIV
4.02k
INRUSH CURRENT 500mA/DIV PWRGD 50V/DIV
PWRGD
4256 TA01
PWRGD UV = 36V OV = 73V PWRGD = 40V
RETRY
U
TM
U
U
LT4256-3 Start-Up Behavior
CONTACT BOUNCE VOUT 50V/DIV
2.5ms/DIV
42563 TA02
42563f
1
LT4256-3
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW UV OV NC OPEN PWRGD NC RETRY GND 1 2 3 4 5 6 7 8 16 VCC 15 SENSE 14 NC 13 GATE 12 VOUT 11 NC 10 FB 9 TIMER
Supply Voltage (VCC) ................................ - 0.3 to 100V SENSE, PWRGD ....................................... - 0.3 to 100V GATE Voltage (Note 2) .................... - 0.3V to VCC + 10V GATE Maximum Current ..................................... 200A VOUT .......................................................... -3V to 100V FB, UV, OPEN ............................................. - 0.3 to 44V OV .............................................................. - 0.3 to 18V RETRY ........................................................ - 0.3 to 15V TIMER Voltage ......................................... - 0.3V to 4.3V Maximum Input Current (TIMER) ....................... 100A Operating Temperature LT4256-3C ............................................. 0C to 70C LT4256-3I ......................................... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER LT4256-3CGN LT4256-3IGN
GN PART MARKING 42563 42563I
GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125C, JA = 130C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 48V unless otherwise noted.
SYMBOL VCC ICC VUVLH VUVHYS IINUV VUVRTH VOVLH VOVHYS IINOV VOPEN VOLOPEN IINOPEN VSENSETRIP IINSNS IPU IPD IPDL VGATE VGATEL PARAMETER Operating Voltage Operating Current Undervoltage Threshold Hysteresis UV Input Current Fault Latch Reset Threshold Voltage Overvoltage Threshold Hysteresis OV Input Current Open-Circuit Voltage Threshold (VCC - VSENSE) OPEN Output Low Voltage Leakage Current SENSE Pin Trip Voltage (VCC - VSENSE) SENSE Pin Input Current GATE Pull-Up Current GATE Pull-Down Current VOUT Pull-Down Current, Fault Condition External N-Channel Gate Drive (Note 2) External N-Channel Gate Drive, Fault Condition IO = 2mA IO = 5mA VOPEN = 5V FB = 0V FB 2V VSENSE = VCC Charge Pump On, VGATE = 7V Any Fault, VGATE > VOUT Any Fault, VGATE = VOUT + VGATEL, VOUT = 48V VGATE - VOUT, 10.8V VCC 20V 20V VCC 80V VGATE - VOUT, VOUT = 48V
q q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS
q
MIN 10.8
TYP 1.8
MAX 80 3.9 4.04 0.55 -1 -3 1.2 4.04 0.55 1 6.5 0.5 1.3 1 22 65 70 - 55 80
UNITS V mA V V A A V V V A mV V V A mV mV A A mA A
VCC Low-to-High Transition UV 1.2V UV = 0V
q
3.96 0.25
4 0.4 -0.1 -1.5
q
0.4 3.96 0.25
0.85 4 0.4 0.1 3 0.20 0.75 0.1
VCC Low-to-High Transition 0V OV < 7V
q
q
1.5
7 45 -16 40
14 55 40 - 30 62 130
4.5 10
8.8 11.6 -2
12.5 12.8
42563f
2
U
V V V
W
U
U
WW
W
LT4256-3
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 48V unless otherwise noted.
SYMBOL VFB VFBHYS VOLPGD IPWRGD IINFB ITIMERPU ITIMERPD VTHTIMER DTIMER VRETRYTH IINRTR tPHLUV tPLHUV tPHLFB tPLHFB tPHLSENSE PARAMETER FB Voltage Threshold FB Hysteresis Voltage PWRGD Output Low Voltage PWRGD Pin Leakage Current FB Input Current TIMER Pull-Up Current TIMER Pull-Down Current TIMER Shutdown Threshold Duty Cycle (RETRY Mode) RETRY Threshold RETRY Input Current UV Low to GATE Low UV High to GATE High FB Low to PWRGD Low FB High to PWRGD High (VCC - VSENSE) High to GATE Low VCC - VSENSE = 275mV RETRY = GND CGATE = 100pF CGATE = 100pF CTIMER = 10nF IO = 1.6mA IO = 5mA VPWRGD = 80V FB = 4.5V
q q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS FB High-to-Low Transition FB Low-to-High Transition
q q
MIN 3.95 4.20 0.3
TYP 3.99 4.45 0.45 0.25 0.60 0.1 -0.1
MAX 4.03 4.65 0.60 0.4 1.0 1 -1 -145 5 5 4.5 1.2 -130 3 9 2 5 3
UNITS V V V V V A A A A V % V A s s s s s
- 85 1.5 4.3 1.5 0.4
- 115 3 4.65 3 0.85 -87 1.7 6 0.8 3.2 1
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
Note 2: An internal clamp limits the GATE pin to a minimum of 10V above VCC. Driving this pin to a voltage beyond the clamp voltage may damage the part.
TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25C unless otherwise noted. SENSE Regulation Voltage vs Temperature
58 FB > 2V SENSE REGULATION VOLTAGE (mV)
53
ICC (mA)
2.0 1.5 1.0
20
ICC (mA)
48
15
FB = 0V
10 -50
-25
0 25 50 TEMPERATURE (C)
UW
75 100
42563 G01
ICC vs VCC
3.5 3.0
2.0 2.5
ICC vs Temperature
VCC = 48V
2.5
1.5
1.0
0.5 0 10 20 30 50 40 VCC (V) 60 70 80
0.5
0 -50
-25
0 25 50 TEMPERATURE (C)
75
100
42563 G03
42563 G02
42563f
3
LT4256-3 TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25C unless otherwise noted. GATE Pull-Up Current vs Temperature
0 GATE PULL-DOWN CURRENT (mA) -5 GATE PULL-UP CURRENT (A) -10 -15 -20 -25 -30 -35 -40 -50 -25 0 25 50 TEMPERATURE (C) 75 100
42563 G04
60 59 58 57 56 -50
IGATE (mA )
VGATE - VOUT Voltage vs Temperature
14 12 VGATE - VOUT VOLTAGE (V) 10 8 6 4 2 0 -50 VCC = 12V VCC = 18V 14.0 13.5 VGATE - VOUT VOLTAGE (V) 13.0
12.0 11.5 11.0 10.5 VCC = 80V
ITIMER (A)
VCC = 10.8V
-25
0 25 50 TEMPERATURE (C)
TIMER Currents vs VCC
5.0
TIMER SHUTDOWN THRESHOLD (V)
PULL-DOWN CURRENT 2.5 0
ITIMER (A)
IUV (A)
-80 PULL-UP CURRENT
-100 -120 -140 10 20
30
50 40 VCC (V)
60
4
UW
75
42563 G06
GATE Pull-Down Current vs Temperature
63 62 61 60 50 40 30 20 10 0 -25 0 25 50 TEMPERATURE (C) 75 100
42563 G05
GATE Pull-Down Capability vs VCC Below Minimum Operating Voltage
0
2
4
6 VCC (V)
8
10
12
42563 G17
VGATE - VOUT Voltage vs Temperature
5.0
TIMER Currents vs Temperature
PULL-DOWN CURRENT 2.5 0 VCC = 20V VCC = 48V -80
12.5
-100 -120 -140 -50
PULL-UP CURRENT
100
10.0 -50
-25
0 25 50 TEMPERATURE (C)
75
100
42563 G07
-25
0 25 50 TEMPERATURE (C)
75
100
42563 G08
TIMER Shutdown Threshold vs Temperature
5.4 5.2 5.0 4.8 4.6 4.4
-1.0 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
UV Current vs UV Voltage
4.2 0 -50
-1.2 -1.4
70
80
-25
0 25 50 TEMPERATURE (C)
75
100
42563 G10
0
1
2
3
4 10 20 30 40 50 VUV (V)
42563 G18
42563 G09
42563f
LT4256-3 TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25C unless otherwise noted. UV Thresholds vs Temperature
4.1 L-H THRESHOLD 4.0 UV THRESHOLDS (V) 3.9 200 150 OV THRESHOLDS (V) 4.0 3.9 3.8 3.7 H-L THRESHOLD 0 -50 -25 0 25 50 TEMPERATURE (C) 75 100
42563 G11
IOV (A)
3.8 3.7 H-L THRESHOLD 3.6 3.5 -50
OPEN Output Voltage vs IOPEN
10 OPEN THRESHOLD VOLTAGE (mV) 9 8 7 VOPEN (V) 6 5 4 3 2 1 0 0 2 4 6 8 IOPEN (mA) 10 12 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5
VPWRGD (V)
FB Thresholds vs Temperature
4.5 4.4 FB THRESHOLDS (V) 4.3 4.2 4.1 4.0 3.9 -50 H-L THRESHOLD L-H THRESHOLD 0.2 0.1 0
IFB (A)
-25
UW
42563 G13
OV Current vs OV Voltage
250 4.1
OV Thresholds vs Temperature
L-H THRESHOLD
100 50
3.6 3.5 -50
0
5
10 VOV (V)
15
20
42563 G19
-25
0 25 50 TEMPERATURE (C)
75
100
42563 G12
OPEN Threshold Voltage vs Temperature
6 5 4 3 2 1 0
PWRGD Output Voltage vs IPWRGD
VCC - VSENSE
0 -50
-25
0 25 50 TEMPERATURE (C)
75
100
42563 G14
0
2
4
6 8 IPWRGD (mA)
10
12
42563 G15
FB Current vs FB Voltage
-0.1 -0.2 -0.3
-0.4 0 25 50 TEMPERATURE (C) 75 100
42563 G16
0
10
20
30 VFB (V)
40
50
42563 G20
42563f
5
LT4256-3
PI FU CTIO S
UV (Pin 1): Undervoltage Sense Input. UV is an input that enables the output voltage. When UV is driven above 4V, GATE will start charging and the output turns on. When UV goes below 3.6V, GATE discharges and the output shuts off. Pulsing UV to below 0.4V for at least 5s after a current limit fault cycle resets the fault latch (when RETRY pin is low, commanding latch off operation) and allows the part to turn back on. This command is only accepted after TIMER is discharged below 0.65V. To disable UV sensing, connect the pin to a voltage between 5V and 44V. OV (Pin 2): Overvoltage Sense Input. OV is an input that disables the output voltage. If OV ever goes above 4V, GATE is discharged and the output shuts off. When OV goes below 3.6V, GATE starts charging and the output turns back on. To disable overvoltage sensing, connect pin to ground. NC (Pins 3, 6, 11, 14): No Connect. Not connected to any internal circuitry. OPEN (Pin 4): Open Circuit Detect Output. This pin is an open collector output that releases and is pulled high through an external resistor if the load current is less than (3mV)/R5. PWRGD (Pin 5): Power Good Output. PWRGD is pulled low whenever the voltage on FB falls below the high-to-low threshold voltage. It goes into a high impedance state when the voltage on FB exceeds the low-to-high threshold voltage. An external pull-up resistor can pull PWRGD to a voltage higher or lower than VCC. RETRY (Pin 7): Current Fault Retry Input. RETRY commands the operational mode of the current limit. If RETRY is floating, the LT4256-3 automatically restarts after a current fault. If it is connected to a voltage below 0.4V, it will latch off after a current fault (which requires that UV be cycled low in order to start normal operation again). GND (Pin 8): Device Ground. This pin must be tied to a ground plane for best performance. TIMER (Pin 9): Timing Input. An external timing capacitor from TIMER to GND programs the maximum time the part is allowed to remain in current limit. When the part goes into current limit, a 115A pull-up current source starts to charge the timing capacitor. When the voltage on TIMER reaches 4.65V (typ), GATE is pulled low; the TIMER pullup current will be turned off and the capacitor is discharged by a 3A pull-down current. When TIMER falls below 0.65V (typ), GATE turns on again if RETRY is high (if RETRY is low, UV must be pulsed low to reset the internal fault latch before GATE will turn on). If RETRY is grounded and UV is not cycled low, GATE remains latched off and TIMER will be discharged to near ground. UV must be cycled low after TIMER has discharged below 0.65V (typ) to reset the part. If RETRY is floating or connected to a voltage above its 1.2V threshold, the LT4256-3 automatically restarts after a current fault. Under an output short-circuit condition, the LT4256-3 cycles on and off with a 3% on-time duty cycle. FB (Pin 10): Power Good Comparator Input. FB monitors the output voltage through an external resistive divider. When the voltage on FB is lower than the high-to-low threshold of 3.99V, PWRGD is pulled low and released when FB is pulled above the 4.45V low-to-high threshold. The voltage present on FB affects foldback current limit (see Figure 8 and related discussion). VOUT (Pin 12): Output Voltage Sense Input. This pin should be connected to the source of the external MOSFET. It is used to sense when the MOSFET is shut off (during any fault mode) and to reduce the pull-down current on GATE. This protects the LT4256-3 from excessive power dissipation when large output capacitors are used.
6
U
U
U
42563f
LT4256-3
PI FU CTIO S
GATE (Pin 13): High Side Gate Drive for the External N-Channel MOSFET. An internal charge pump guarantees at least 10V of gate drive for VCC supply voltages above 20V and 4.5V of gate drive for VCC supply voltages between 10.8V and 20V. The rising slope of the voltage on GATE is set by an external capacitor connected from GATE to GND and an internal 30A pull-up current source from the charge pump output. If the current limit is reached, the GATE voltage is adjusted to maintain a constant voltage across the sense resistor while the timing capacitor starts to charge. If the TIMER voltage ever exceeds 4.65V, GATE is pulled low. GATE is also pulled to GND whenever UV is pulled low; the VCC supply voltage drops below the externally programmed undervoltage threshold, above the overvoltage threshold or below the internal UVLO threshold (9.8V). GATE is clamped internally to a maximum voltage of 11.6V (typ) above VOUT under normal operating conditions. Driving this pin beyond the clamp voltage may damage the part. GATE is also clamped to 2V (typ) below VOUT. When the gate is commanded off due to a fault condition, it is discharged quickly by a 62mA (typ) capable switch until GATE is 2V (typ) below VOUT. When GATE is below VOUT by 2V, the 62mA is reduced to 130A to protect the LT4256-3 against damage if VOUT has large capacitance. A Zener diode is needed between the gate and source of the external MOSFET to protect its gate oxide under instantaneous short-circuit conditions. See Applications Information. SENSE (Pin 15): Current Limit Sense Input. A sense resistor is placed in the supply path between V CC and SENSE. The current limit circuit regulates the voltage across the sense resistor (VCC - SENSE) to 55mV while in current limit when FB is 2V or higher. If FB drops below 2V, the regulated voltage across the sense resistor decreases linearly and stops at 14mV when FB is 0V. The OPEN output also uses SENSE to detect when the output current is less than (3mV)/R5. To defeat current limit, connect SENSE to VCC. VCC (Pin 16): Input Supply Voltage. The positive supply input ranges from 10.8V to 80V for normal operation. ICC is typically 1.8mA. An internal circuit disables the LT4256-3 for inputs less than 9.8V (typ).
U
U
U
42563f
7
LT4256-3
BLOCK DIAGRA
VCC 16
VP GEN FB 10
REF GEN 4V 7V 100k RETRY UV OV VCC 7 1 2
9.8V
0.65V
4.65V
8
W
SENSE 15
+
3mV OPEN CIRCUIT 4 OPEN
-
VP
-
14mV TO 55mV CURRENT LIMIT
+ +
FOLDBACK 2V
CHARGE PUMP AND GATE DRIVER
12 VOUT 13 GATE
-
4V
+
5 PWRGD
-
-
INTERNAL UV
+
4V
-
UV LOGIC
+
TIMER LOW
+
VP OV 118A
-
4V
- +
+
TIMER HIGH
-
9
TIMER
3A 8 GND
4256 BD
42563f
LT4256-3
TEST CIRCUIT
PWRGD OPEN FB VCC SENSE GATE VOUT TIMER RETRY GND 3V 48V 100pF 48V
+-
-+
3V
OV UV
+-
+-
4256 F01
Figure 1
TI I G DIAGRA S
4V UV tPLHUV 3.6V tPHLUV
W
UW
GATE 2V
2V
4256 F02
Figure 2. UV to GATE Timing
4V FB tPLHFB
3.65V tPHLFB
PWRGD
1V
1V
4256 F03
Figure 3. VOUT to PWRGD Timing
VCC - SENSE
55mV tPHLSENSE VCC
4256 F04
GATE
Figure 4. SENSE to GATE Timing
42563f
9
LT4256-3
APPLICATIO S I FOR ATIO
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the supply bypass capacitors on the boards draw high peak currents from the backplane power bus as they charge. The transient currents can permanently damage the connector pins and glitch the system supply, causing other boards in the system to reset. The LT4256-3 is designed to turn on a board's supply voltage in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The device also provides undervoltage and overvoltage as well as overcurrent protection while a power good output signal indicates when the output supply voltage is ready with a high output. Power-Up Sequence An external N-channel MOSFET pass transistor (Q1) is placed in the power path to control the power up of the supply voltage (Figure 5). Resistor R5 provides current detection and capacitor C1 controls the GATE slew rate. Resistor R7 compensates the current control loop while R6 prevents high frequency oscillations in Q1.
VIN 48V (SHORT PIN)
D2 SMAT70A 16 R1 64.9k VCC 1 UV 15 SENSE GATE LT4256-3 13 R6 10 R7 100 C1 10nF
C3 0.01F
R2 4.02k R3 4.02k
2
OV
4 9 GND C2 33nF
OPEN TIMER
Figure 5. 1.6A, 48V Latchoff Application
10
U
When the power pins first make contact, transistor Q1 is held off. If the voltage on VCC is between the externally programmed undervoltage and overvoltage thresholds, VCC is above 9.8V and the voltage on TIMER is less than 4.65V (typ), transistor Q1 will be turned on (Figure 6). The voltage on GATE rises with a slope equal to 30A/C1 and the supply inrush current is set at: IINRUSH = CL * 30A/C1 where CL is the total load capacitance. (1)
IOUT 500mA/DIV PWRGD 50V/DIV VOUT 50V/DIV GATE 50V/DIV 5ms/DIV
4256 F06
W
U
U
Figure 6. Start-Up Waveforms
R5 0.025
Q1 IRF530 D1 CMPZ5241BS 11V R8 36.5k R4 51k
+
CL
VOUT 48V 1.6A
VOUT FB RETRY PWRGD GND 8
12 10 7 5
R9 4.02k PWRGD
4256 F05
UV = 36V OV = 73V PWRGD = 40V
42563f
LT4256-3
APPLICATIO S I FOR ATIO
To reduce inrush current, increase C1 or decrease load capacitance. If the voltage across the current sense resistor R5 reaches VSENSETRIP, the inrush current will be limited by the internal current limit circuitry. The voltage on GATE is adjusted to maintain a constant voltage across the sense resistor and TIMER begins to charge. When the FB voltage goes above the low-to-high VFB threshold, PWRGD goes high. Undervoltage and Overvoltage Detection The LT4256-3 uses UV and OV to monitor the VCC voltage to determine when it is safe to turn on the load and allow the user the greatest flexibility for setting the operational thresholds. UV and OV are internally connected to an analog window comparator. Any time that UV goes below 3.6V or OV goes above 4V, GATE will be pulled low until the UV/OV voltages return to the normal operation voltage window (4V and 3.6V, respectively). The UV threshold should never be set below the internal UVLO threshold (9.8V typically) because the benefit of the UV's hysteresis will be lost, making the LT4256-3 more susceptible to noise (VCC must be at least 9.8V when UV is at its 3.6V threshold). UV is filtered with C3 to prevent
R5 0.010 D2 SMAT70A 16 R1 64.9k 1 OFF SIGNAL FROM MPU Q2 VN2222 C3 0.01F R2 4.02k 2 R3 4.02k OV UV VCC
VCC 48V (SHORT PIN)
GND
Figure 7. How to Use a Logic Signal to Control the LT4256-3 Turn On/Off
U
noise spikes and capacitively coupled glitches from shutting down the LT4256-3 output erroneously. To calculate UV and OV thresholds, use the following equations: V R1 = (R2 + R3) THUVLH - 1 4V R1 + R2 R3 = VTHOVLH -1 4 20k R1 + R2 + R3 200k R1 VTHUVHL = 3.6 V 1 + ; R2 + R3 R1 + R2 VTHOVHL = 3.6 V 1 + R3 where VTHULH and VTHOVLH are the desired UV and OV threshold voltages when VCC is rising (L - H). Figure 7 shows how the LT4256-3 is commanded to shut off with a logic signal. This is accomplished by pulling the gate of the open-drain MOSFET, Q2, (tied to UV) high.
Q1 IRF540 D1 CMPZ5241BS 11V R6 10 R7 100 C1 10nF R4 51k R8 36.5k
W
U
U
(2a) (2b) (3) (4)
+
CL
VOUT 48V 4A
15 SENSE GATE 13
LT4256-3
VOUT FB
12 10 7 5
4 9
OPEN TIMER
RETRY PWRGD GND 8
R9 4.02k
C2 33nF
4256 F07
UV = 36V OV = 73V PWRGD = 40V
42563f
11
LT4256-3
APPLICATIO S I FOR ATIO
Short-Circuit Protection
The LT4256-3 features a programmable foldback current limit with an electronic circuit breaker that protects against short circuits or excessive load currents. The current limit is set by placing a sense resistor (R5) between VCC and SENSE. The current limit threshold is calculated as: ILIMIT = 55mV/R5 (5) To limit excessive power dissipation in the pass transistor and to reduce voltage spikes on the input supply during short-circuit conditions at the output, the current folds back as a function of the output voltage, which is sensed internally on FB. If the LT4256-3 goes into current limit when the voltage on FB is 0V, the current limit circuit drives GATE to force a constant 14mV drop across the sense resistor. As the output at FB increases, the voltage across the sense resistor increases until FB reaches 2V, at which point the
VCC - VSENSE
55mV
RESPONSE TIME (s)
14mV
0V
2V
FB
4256 F08
Figure 8. Current Limit Sense Voltage vs Feedback Pin Voltage
12
U
voltage across the sense resistor is held constant at 55mV (see Figure 8). For a 0.025 sense resistor, the typical current limit is set at 2200mA and folds back to 560mA when the output is shorted to ground. Thus, MOSFET peak power dissipation under short-circuit conditions is reduced from 106W to 27W. See the Layout Considerations section for important information about board layout to minimize current limit threshold error. The LT4256-3 also features a variable overcurrent response time. The time required for the part to regulate the GATE voltage is a function of the voltage across the sense resistor connected between VCC and SENSE. This helps to eliminate sensitivity to current spikes and transients that might otherwise unnecessarily trigger a current limit response and increase MOSFET dissipation. Figure 9 shows the response time as a function of the overdrive at SENSE.
12 10 8 6 4 2 0 50 100 150 VCC - VSENSE (mV) 200
4256 F09
W
U
U
Figure 9. Response Time to Overcurrent
42563f
LT4256-3
APPLICATIO S I FOR ATIO
TIMER
TIMER provides a method for programming the maximum time the part is allowed to operate in current limit. When the current limit circuitry is not active, TIMER is pulled to GND by a 3A current source. When the current limit circuitry becomes active, a 118A pull-up current source is connected to TIMER and the voltage will rise with a slope equal to 115A/CTIMER as long as the circuitry stays active. Once the desired maximum current limit time is known, the capacitor value is: C[nF ] = 25 * t[ms]; C = 115A *t 4.65V (6)
Whenever TIMER reaches 4.65V (typ), the internal fault latch is set causing GATE to be pulled low and TIMER to be discharged to GND by the 3A current source. The part is not allowed to turn on again until the voltage on TIMER falls below 0.65V (typ). Whenever GATE is commanded off by any fault condition, it is discharged with a high current, turning off the external MOSFET. The waveform in Figure 10 shows how the output latches off following a current fault. The drop
IOUT 500mA/DIV
TIMER 5V/DIV
VOUT 50V/DIV
GATE 50V/DIV 10ms/DIV
4256 F10
Figure 10. Latch Off Waveforms
U
across the sense resistor is held at 55mV as the timer ramps up. Once TIMER reaches its shutdown threshold (4.65V typically), the circuit latches off. Automatic Restart If RETRY is floating, then the device automatically restarts after a current overload fault. When the voltage at TIMER ramps back down to 0.65V (typ), the LT4256-3 turns on again. If the short-circuit condition at the output still exists, the cycle will repeat itself indefinitely. The duty cycle under short-circuit conditions is 3% which prevents Q1 from overheating. Figure 11 shows representative waveforms during a short circuit. Latch Off Operation If RETRY is grounded, the LT4256-3 will latch off after a current fault. After the part latches off, it may be commanded to start back up. This is accomplished by cycling UV to ground and then back high (this command can only be accepted after TIMER discharges below the 0.65V typ threshold, which prevents overheating transistor Q1).
IOUT 500mA/DIV TIMER 5V/DIV VOUT 50V/DIV GATE 50V/DIV 10ms/DIV
4256 F11
W
U
U
Figure 11. RETRY Waveforms
42563f
13
LT4256-3
APPLICATIO S I FOR ATIO
Therefore, using RETRY only, the LT4256-3 will either latch off after an overcurrent fault condition or it will go into a hiccup mode. Power Good Detection The LT4256-3 includes a comparator for monitoring the output voltage. The output voltage is sensed through the FB pin via an external resistor string. The comparator's output (PWRGD) is an open collector capable of operating from a pull-up as high as 80V. PWRGD can be used to directly enable/disable a power module with an active high enable input. Figure 12 shows how to use PWRGD to control an active low enable input power module. Signal inversion is accomplished by transistor Q2 and R10. The thresholds for the FB pin are 4.45V (low to high) and 3.99V (high to low). To calculate the PWRGD thresholds, use the following equations:
VCC 24V (SHORT PIN)
D2 SMAT70A 16 R1 32.4k 1 UV VCC 15 SENSE GATE LT4256-3 12 10 7 5 R9 4.02k 13 R6 10 R7 100 C1 10nF
C3 0.01F
R2 4.02k
2 R3 4.02k 4 9 GND C2 33nF
OV OPEN TIMER
Figure 12. Active Low Enable PWRGD Application
14
U
V R8 = THPWRGD - 1 * R9, high to low 3.99 V 20k R8 + R9 200k R8 VTHPWRGD = 4.45V 1+ , low to high R9 OPEN Pin/Open FET Detection OPEN is an output which signals abnormally low load currents. When the voltage across the sense resistor is less than 3mV, the open collector pull-down device is shut off allowing OPEN to be externally pulled high. OPEN is always active when VCC is above 9.8V. If VCC is below 9.8V (the internal UVLO threshold), OPEN is pulled low. Open-circuit MOSFETs are detected with the LT4256-3 by monitoring the voltage across R5 with OPEN while monitoring the output voltage with PWRGD. An open FET condition is signalled when OPEN is high and PWRGD is low (after the part has completed its start-up cycle). (7) (8a) (8b)
R5 100m Q1 IRFZ34VS D1 CMPZ5241BS 11V
W
U
U
+
CL
VOUT 24V 400mA
VLOGIC R10 51k
VOUT FB RETRY PWRGD GND 8
R8 14k R4 27k
PWRGD
UV = 20V OV = 40V PWRGD = 18V
Q2 ZN3904
4256 F12
42563f
LT4256-3
APPLICATIO S I FOR ATIO
This open FET condition can be falsely signalled during start-up if the load is not activated until after PWRGD goes high. To avoid this false indication, OPEN and PWRGD should not be polled for a period of time, tSTARTUP, given by:
tSTARTUP = 3 * VCC * C1 30A
This can be accomplished either by a microcontroller (if available) or by placing an RC filter as shown in Figure 13. Once the OPEN voltage exceeds the monitoring logic threshold, VTHRESH, and PWRGD is low, an open FET condition is signalled. In order to prevent a false indication, the RC product should be set with the following equation:
RC >
3 * VCC * C1 VLOGIC 30Aln VLOGIC - VTHRESH
Another condition that can cause a false indication is if the LT4256-3 goes into current limit during start-up. This will cause tSTARTUP to be longer than calculated. Also, if the LT4256-3 stays in current limit long enough for TIMER to fully charge up to its threshold, the LT4256-3 will either latch off (RETRY = 0) or go into the current limit hiccup mode (RETRY = floating). In either case, an open FET condition will be falsely signalled. If the LT4256-3 does go into current limit during start-up, C1 can be increased (see Power-Up Sequence).
VGATE (V)
TO MONITORING LOGIC
VLOGIC LT4256-3 OPEN INTERNAL OPEN COLLECTOR PULL-DOWN 4 C
4256 F13
R
Figure 13. Delay Circuit for OPEN FET Detection
U
Supply Transient Protection The LT4256-3 is 100% tested and guaranteed to be safe from damage with supply voltages up to 80V. However, voltage transients above 100V may cause permanent damage. During a short-circuit condition, the large change in currents flowing through the power supply traces can cause inductive voltage transients which could exceed 100V. To minimize the voltage transients, the power trace parasitic inductance should be minimized by using wider traces or heavier trace plating and a bypass capacitor should be placed between VCC and GND. A surge suppressor (TransZorb(R)) at the input can also prevent damage from voltage transients. GATE Pin A curve of gate drive vs VCC is shown in Figure 14. GATE is clamped to a maximum voltage of 12.8V above VOUT. This clamp is designed to withstand the internal charge pump current. An external Zener diode must be used as shown in all applications. At a minimum input supply voltage of 10.8V, the minimum gate drive voltage is 4.5V. When the input supply voltage is higher than 20V, the gate drive voltage is at least 10V and a standard threshold MOSFET can be used. In applications from 12V to 15V range, a logic level MOSFET must be used.
TransZorb is a registered trademark of General Instruments, GSI.
13 12 11 10 9 8 7 6 5 4 3 10 20 30 50 40 VCC (V) 60 70 80
4256 F14
W
U
U
(9)
(10)
Figure 14. VGATE vs VCC
42563f
15
LT4256-3
APPLICATIO S I FOR ATIO
In some applications it may be possible for VOUT to ring below ground (due to the parasitic trace inductance). Higher current applications, especially where the output load is physically far away from the LT4256-3 will be more susceptible to these transients. This is normal and the LT4256-3 has been designed to allow for some ringing below ground. However, if the application is such that VOUT can ring more than 3V below ground, damage may occur to the LT4256-3 and an external diode, D2, from ground (anode) to VOUT (cathode) will have to be added to the circuit as shown in Figure 15 (it is critical that the reverse breakdown voltage of the diode be higher than the highest expected VCC voltage). A capacitor placed from ground to VOUT directly at the LT4256-3 pins can help reduce the amount of ringing on VOUT but it may not be enough for some applications. During a fault condition, the LT4256-3 pulls down on GATE with a switch capable of sinking about 62mA. Once GATE drops below the output voltage by a diode forward voltage, the external Zener will forward bias and VOUT will also be discharged to GND. In addition to the GATE capacitance, the output capacitance will be discharged through the LT4256-3. In applications utilizing very large external N-channel MOSFETs, the possibility exists for the MOSFET to turn on when initially inserted into a live backplane (before the
R5 0.010 D2 SMAT70A 16 R1 64.9k 1 C3 0.01F R2 4.02k UV VCC 15 SENSE GATE LT4256-3 12 10 7 5 13
VCC 48V (SHORT PIN)
2 R3 4.02k 4 9 GND C2 33nF
OV OPEN TIMER
Figure 15. Negative Output Voltage Protection Diode Application
42563f
16
U
LT4256-3 becomes active and pulls down on GATE). This is due to the MOSFET intrinsic drain to gate capacitance forcing current into R7 and C1 when the drain voltage steps up from ground to VCC with an extremely fast rise time. To alleviate this situation, a diode, D3, should be put across R7 with the cathode connected to C1 as shown in Figure 16. Whenever the LT4256-3 turns the MOSFET off, GATE pulls the MOSFET gate to ground with an open collector capable of sinking 62mA. If the output is held up by a large reservoir capacitor, the stored energy is dissipated in the pull-down transistor via a sneak path through the (now forward biased) Zener, D1. The LT4256-3 has a proprietary feature that reduces on-chip power dissipation by sensing when the MOSFET is off and reducing the pulldown current significantly. See VGATE Turn-Off for more information about using this feature. VGATE Turn-Off The LT4256-3 has a proprietary feature that reduces power dissipation by sensing when the MOSFET is off and reducing the pull-down current significantly. As the GATE pin is discharged during any fault, the LT4256-3 monitors the GATE pin and VOUT pin. When the GATE pin is 2V below VOUT, the pull-down current is reduced from 62mA to about 130A.
Q1 IRF540 D1 CMPZ5241BS 11V R6 10 R7 100 C1 10nF R8 36.5k
W
U
U
+
CL
VOUT 48V 4A
D3 MRA4003T3
VOUT FB RETRY PWRGD GND 8
R9 4.02k
R4 51k
4256 F14
UV = 36V OV = 73V PWRGD = 40V
LT4256-3
APPLICATIO S I FOR ATIO
In order to use this feature as designed, a bidirectional Zener diode is needed for D1. When the LT4256-3 commands the MOSFET off (and a bidirectional Zener is used), the output discharges very slowly (tOFF = (CLOAD * VOUT)/ 130A). Several variations can be implemented to discharge the output faster. The recommeded method is shown in Figure 17 and uses an external PNP transistor, diode and resistor to discharge the output quickly.
R5 0.033 D2 SMAT70A 16 R1 64.9k 1 C3 0.1F R2 4.02k UV VCC 15 SENSE GATE 13
VCC 48V (SHORT PIN)
2 R3 4.02k 4 9 GND C2 33nF
OV
OPEN TIMER
Figure 16. High dV/dt MOSFET Turn-On Protection Circuit
R5 0.010 D2 SMAT70A 16 R1 64.9k 1 C3 0.01F R2 4.02k 2 R3 4.02k FB 4 9 GND C2 33nF OPEN TIMER RETRY PWRGD GND 8 OV UV VCC 15 SENSE GATE LT4256-3 13 R7 100 C1 10nF R8 36.5k R9 4.02k R4 51k R6 1k Q1 IRF540 D1 CMPZ5241BS 11V RB 18k D3 1N4148 RPROG VOUT 48V 4A CL
VCC 48V (SHORT PIN)
Figure 17. Enhanced Output Pull-Down Circuit
42563f
U
The equation to set the nominal discharge current is:
W
U
U
5000 (130A) RPROG where RPROG must be less than 1k. IDISCHG =
The maximum current equation is:
(11)
IMAX =
Q1 IRF530
7000 (350A) RPROG
VOUT 48V 1.2A
(12)
D1 CMPZ5241BS 11V R6 10 D3 1N4148W R8 36.5k
+
CL
LT4256-3
R7 100 C1 10nF
VOUT FB RETRY PWRGD GND 8
12 10 7 5
R9 4.02k
4256 F16
R4 27k
UV = 36V OV = 73V PWRGD = 40V
+
Q2 2N4920
VOUT
12
10 7 5
4256 F17
UV = 36V OV = 73V PWRGD = 40V
17
LT4256-3
APPLICATIO S I FOR ATIO
Layout Considerations
To achieve accurate current sensing, a Kelvin connection to the current sense resistor (R5 in typical application circuit) is recommended. Note that 1oz copper exhibits a sheet resistance of about 530/ . Small resistances can cause large errors in high current applications. Noise
VIN R6
D2 R2
R1 VOUT R7 LT4256-3 R3 R8 R9 GND C1
Figure 18. Recommended Component Placement
18
U
immunity will be improved significantly by locating resistor dividers close to the pins with short VCC and GND traces. The minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. 0.03" per amp or wider is recommended. Figure 18 shows a layout that meets these requirements.
D1 Q1 R5
42563 F18
W
U
U
42563f
LT4256-3
PACKAGE DESCRIPTIO U
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005 .189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF .150 - .165 .229 - .244 (5.817 - 6.198) .0165 .0015 .150 - .157** (3.810 - 3.988) .0250 BSC 1 .015 .004 x 45 (0.38 0.10) .007 - .0098 (0.178 - 0.249) .016 - .050 (0.406 - 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP .0532 - .0688 (1.35 - 1.75) 23 4 56 7 8 .004 - .0098 (0.102 - 0.249) .008 - .012 (0.203 - 0.305) TYP .0250 (0.635) BSC
GN16 (SSOP) 0204
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
42563f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT4256-3
APPLICATIO S I FOR ATIO
R5 0.020 Q2 IRF540
Dual 48V Supply Sequencing Application
VOUT2 48V 2A
D3 CMPZ5241BS 11V R1 64.9k UV C3 0.01F R2 4.02k OV R3 4.02k OPEN TIMER 33nF GND PWRGD RETRY UV = 36V OV = 73V PWRGD = 40V VCC SENSE R6 10 C1 R7 10nF 100 R8 36.5k
GATE LT4256-3 VOUT FB
VIN 48V (SHORT PIN) R1 64.9k
R5 0.020 D2 SMAT70A VCC UV C3 0.01F R2 4.02k OV R3 4.02k C2 33nF OPEN TIMER GND PWRGD SENSE
Q1 IRF540 D1 CMPZ5241BS 11V R6 10 C1 R7 10nF 100 R8 36.5k
GATE LT4256-3 VOUT FB
RETRY
GND
UV = 36V OV = 73V PWRGD = 40V
RELATED PARTS
PART NUMBER LT1641-1/LT1641-2 LTC4211 LTC4251 DESCRIPTION Positive 48V Hot Swap Controller in SO-8 - 48V Hot Swap Controller in SOT-23 COMMENTS 9V to 80V Operation, Active Current Limit, Autoretry/Latchoff Floating Supply from -15V, Active Current Limiting, Fast Circuit Breaker Floating Supply from -15V, Active Current Limiting, Power Good Output Floating Supply from -15V, Active Current Limiting, Enables Three DC/DC Converters 10.8V to 36V Operation, Open-Circuit Detection 10.8V to 80V Operation, Active Current Limit, Autoretry/Latchoff Single Hot Swap Controller with Multifunction Current Control 2.5V to 16.5V, Active Inrush Limiting, Dual Level Cicuit Breaker
LTC4252-1/LTC4252-2 - 48V Hot Swap Controller in MSOP LTC4253 LT4254 LT4256-1/LT4256-2 - 48V Hot Swap Controller and Supply Sequencer Positive High Voltage Hot Swap Controller Positive High Voltage Hot Swap Controller
20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
www.linear.com
U
+
CL2 R4 51k R9 4.02k
VIN 50V/DIV
W
U
U
PWRGD2
VOUT1 50V/DIV
+
CL1
VOUT1 48V 2A
PWRGD1 50V/DIV
R4 51k
VOUT2 50V/DIV 5ms/DIV
4256 TA04
R9 4.02k
PWRGD1
4256 TA03
42563f LT/TP 0304 1K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2004

▲Up To Search▲

Price & Availability of LT4256-3

	To Download LT4256-3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .